Vlsi Design Overview

Principles

Definition

Vlsi design is a multidisciplinary research field and methodological approach concerned with the conceptualization, implementation, and verification of integrated circuits containing a very high density of electronic components. It investigates the principles, techniques, and automation tools necessary to translate complex system-level specifications into manufacturable silicon layouts, encompassing aspects from circuit architecture and logic design to physical layout and testing, fundamentally enabling modern electronic technologies.

Ontological type

CAD Tools and Flows

Verification and Testing

Design Methodologies

Key developments

Key Figures

Manufacturability and Interconnect era

Mark Horowitz [1] is associated with Stanford University [3] and University of Georgia [4] during the Manufacturability and Interconnect era. His notable contribution is the paper Signal Delay in RC Tree Networks [5] (1983), which analyzed RC delays in interconnect trees and helped drive RC-aware timing analysis and layout rules essential to this era. T.W. Williams [2] is associated with Stanford University [3] and University of Georgia [4] in this era. His key contribution A logic design structure for LSI testability [6] (1977) introduced a framework for testability in LSI designs, enabling fault isolation and supporting manufacturability under interconnect constraints in this era.

Timing and Power Optimization era

Mark Horowitz [1] was a leading figure at Stanford University [3] and State University of New York [4] during the Timing and Power Optimization era. His contributions include Supply and threshold voltage scaling for low power CMOS [8] and The future of wires [7], which were pivotal for integrating power-aware voltage scaling with interconnect-aware timing in CAD workflows during that era. Andrew B. Kahng [2] contributed from University of California, San Diego [5] and University of California, Los Angeles [6]. His work on New spectral methods for ratio cut partitioning and clustering [9] offered scalable graph-partitioning techniques that underpinned hierarchical CAD and interconnect-aware optimization in timing-power design during Timing and Power Optimization.

Variability-Resilient Energy Scaling era

Dean M. Tullsen [1] was associated with the University of California, San Diego [3] and the University of Washington [4] during this era. His key contribution in this era stems from McPAT [7], a power, area, and timing modeling framework that enables energy- and performance-aware exploration of variability-resilient designs. Norman P. Jouppi [2] has ties to Seoul National University [5] and The University of Texas at Austin [6] during this era. For Norman P. Jouppi [2], McPAT [7] provided a standardized power modeling approach that accelerated energy-aware design-space exploration and resilience to variability across architectures.